Liberty File Format

Greetings!!! :)

In this blog I have tried to provide information regarding cell library file. It contains 3 sections namely: Introduction to Liberty File, Contents of Liberty file and finally an example of Liberty file. Hope this information might be helpful for readers.

Introduction to Liberty File:

From previous blog, one can conclude that .v, LEF and DEF files merely contains information regarding logic connectivity and physical attributes of all the objects (cells, nets, pins, etc.). Still many important information, such as cell propagation delay, cell leakage and dynamic power consumption, noise margin, etc. is missing which is used to analyze and optimize PPA (Performance, Power and Area) parameters of design. These information can be obtained from cell library file which gives detailed information about cell behaviour. Here cell can be a standard cell or any complex IPs.

A library file contains important information such as timing, power, input and output characteristics, environmental conditions (PVT), and noise margin of cells. This cell behaviour is characterized by performing Monte Carlo simulation in SPICE tools. There are several formats available to represent these simulations results but most widely accepted format across semiconductor industry is Liberty file format. It is an open-source file format developed by Synopsys Inc. It is also backed by IEEE Industry Standards and Technology Organization (IEEE-ISTO).

Cell library file is technology specific and is provided by foundry or IP vendor. It is written in human readable ASCII format. There can be a separate lib file for each scenario defined in the design. This file comes with extension .lib.

Content in Liberty File:

Sections defined within liberty file are as below:

• Library header

  • First line in library file is the library name followed by technology name and delay model.

  • PVT operating conditions

    • nom_process : FF, SS, TT

    • nom_temperature : temperature at which library is characterized

    • nom_voltage : voltage at which library is characterized

  • Unit definition for time, voltage, current, resistance, capacitance, leakage power.

• Cell related statements

  • Cell name

  • Cell area

  • Cell leakage power (leakage power is represented in form of look-up table)

• Cell footprint

• Pin related statements

  • pin direction (in, out, inout)

  • unate (positive, negative or no-unate)

  • Pin type (signal, clock, power, ground)

  • Pin delay (rise and fall delay, rise and fall transition)

  • Functionality

  • Pin capacitance

  • Internal power

• Wire load model

  • Defined in the form of look-up table (lut).

  • Delay values are calculated based upon input transition delay and output load.

• Power look-up table template

Example of Liberty File Format:

Below snippet shows an example of how Liberty file looks like. It is not necessary that units or attributes shown in below example are same in all Liberty files. It changes with technology and design parameters.

library ("std_cell library") {
    technology ("my_technology");
    delay_model : state which delay model is used in delay calculation;
    routing_layers (name all layers);
    time_unit : ns ;
    voltage_unit : V ;
    current_unit : mA ;
    pulling_resistance_unit : kohm ;
    capacitance_load_unit : pF ;
    leakage_power_unit : nW ;
    
    operating_conditions ("NORM") {
        process : 1
        temperature : 25
        voltage : 1.0
    }
    
    timing_range (name) {
        #timing information
    }
    
    wire_load_model (name) {
        #wire load table
    }
    
    power_lut_template (name) {
        #power look-up table
    }
    
    cell ("AND") {
        #cell functionality, area, delay and power attributes
        pin ("Z") {
            #pin direction, type, metal layer, rise_time, fall_time,        
            rise_transition, fall_transition, pin delay, capacitance,
            etc.
        }
    }
}