SDC File

Synopsys Design Constraint (SDC) file defines the timing constraints of the design. Timing constraints are needed to perform timing analysis and optimisation. Tool does not calculate timing for the paths for which timing constraint is not defined. SDC file is a simple text file written in TCL format. Commands written in SDC files are general i.e. not specific to any tool. SDC file can be created by simply writing commands in a text file or one can use tools available to generate SDC file. Extension of SDC file is .sdc .

SDC file has 3 sections as below.

Header Section (optional)

• It contains information related to SDC version and units for resistance, capacitance, voltage, power, time, etc.

• If SDC file is generated using a tool then date and time of file generation is also available in header section.

Commands Section

• SDC commands can be broadly classified into 5 categories which are

1. General commands (set_units, set_hierarchy_separator, etc.)

2. Object selection commands (get_cells, get_pins, get_clocks, all_clocks, all_inputs, all_outputs, etc.)

3. Timing constraints (create_clock, create_generated_clock, group_path, set_clock_groups, set_input_delay, set_output_delay, set_clock_transition, set_clock_latency, set_clock_uncertainty, set_false_path, set_multicycle_path, etc.)

4. Environment commands to set PVT scenarios and design verification rules (set_operating_condition, set_max_fanout, set_max_transition, set_max_capacitance, set_wire_load_model, etc.)

5. Multi-voltage commands (create_voltage_area, set_max_dynamic_power, set_max_leakage_power, etc.)

Comment Section (optional)

• Comments in SDC file start with symbol # and terminates automatically at the end-of-line.

• Comments are written either in order to pass some information regarding usage of commands or for future reference.

Few important points to be remembered about SDC file are:

• There is separate SDC file for each scenario in the design.

• SDC file for floorplanning and placement stage is different than that of CTS and later stages. Reason being clock is ideal till placement so all the clock delays are modelled into clock uncertainty command but once CTS is build clock uncertainty value has to be reduced. After CTS clock uncertainty only models the jitter value, other delays will be the actual delay.

• If timing constraint for any I/O port or logic path is missing in the SDC file then tool will not perform timing analysis for that particular path which can lead to highly optimistic timing reports. Thus it is highly important to check for missing constraints, if found any then should be fixed on the highest priority.

This post gives a brief understanding about SDC file. To know more or if you have any query feel free to contact or mention in comment section below.

To read more about Physical Design concepts please refer to below link.

https://www.physicaldesigninsight.com/blog/categories/physical-design