Greetings Readers...!
This blog mainly focuses on four topics which are:
Types of Cells
Significance and types of placement bounds
Significance and types of placement blockages
Significance and types of cell padding or keepout margin
Types of Cells
i. Standard Cells :
These are the logic cells defined in netlist. For eg. logic gates and registers.
ii. END CAP Cells :
Usually placed at all the four edges, and at the corners of the block. End cap cells are marked as the end of the row.
Its main purpose is to protect standard from damaging during fabrication process. Cells at the edges are more vulnerable to damage because of laser cutting process during fabrication.
Another objective of using end cap cells is to overcome spacing DRC violation related to poly and implant layer at the edges. End cap cells also provide necessary isolation between two blocks when integrated at the top level.
There are distinct cells defined in library for right edge, left edge, top edge, bottom edge, the corners. Appropriate cells should be placed at particular edge otherwise it can lead to DRC violations.
iii. WELL TAP Cells :
Well TAP cells are used to connect p-substrate to VSS and n-well to VDD. Main purpose of using well tap cell is to prevent latch-up issue.
TAP cells offer a low resistance path for current to flow hence preventing latch-up issue to occur.
These cells are placed at a particular distance, as per rules provided by foundry, in the block.
At higher technology node, tap connections were provided inside the standard cells itself but as technology advanced, standard cell size got shrink. So tap connections are removed from the standard cells to reduce its size and TAP cells are provided separately in the library.
iv. TIE Cells :
There are two types of TIE cells : Tie-high and Tie-low cells.
Tie-high cell is used to connect the gate terminal of a transistor to VDD (logic 1) whereas Tie-low cell is used to connect the gate terminal of a transistor to VSS (logic 0).
At lower technology node, gate terminal is very thin and also device threshold voltage is very low. So connecting the transistor input directly to VDD or VSS can turn on transistor with a little power/ground bounce. In worst case, more power can damage gate terminal as well. Hence tie cells are used to connect standard cell's input to PG rails and protect them from damaging.
v. DECAP Cells :
Decoupling capacitor cells also known as DECAP cells are power storage cells.
DECAP cell functions as a capacitor which stores power in it. Whenever there is large current requirement in the design, DECAP cell discharges itself and supply power to the logic cells or macros in the design. Once discharged it can be charged again using power and ground rail and can supply power whenever required.
It is placed between power and ground stripes.
More number of DECAP cells can be used if there is power hungry IP used in the design.
It acts as one of the prevention for dynamic IR drop.
vii. FILLER Cells :
As the name suggest, FILLER cells are used to fill the gaps between standard cells. Major role of FILLER cells is to provide n-well and implant layer continuity.
There are certain spacing rules for n-well and implant layers. To satisfy these rules standard cells have to be placed at certain distance apart. This can lead to increased chip size which is not a feasible idea. Solution to this is to make n-well and implant layer continuous through out each row in the block. For this FILLER cells are used.
While inserting filler cells, filler cell with the largest size available is inserted first then smaller cells are used. This approach is followed so that block can be filled with as minimum number of filler cells as possible.
viii. SPARE Cells :
Spare cells are the additional cells spread across the block.
These are logic cells which are not defined in netlist but can be used if there is any functionality update in the design.
Spare cells proves to be very useful if there is any functionality change after base tape out. During base tape out all the standard cells in design will be freeze so we cannot add new cells even if there is any functionality change. At this time spare cells can be used.
Spare cells will be floating as its output is not connected to any logic unless there is any requirement to use spare cells.
ix. Integrated Clock Gating (ICG) Cells :
ICG cells are used to save dynamic power by turning off the clock network when not in use.
Simple AND gate can be used along with a latch as ICG cell to control the clock network as shown in figure 1.
Here AND gate is latched in order to perform the gating operation in sync with the clock. Enable (EN) pins is used to turn-on or off the ICG cell.
Output network shown by the series of D flip-flop will be turned off if EN pin of ICG cell is set to logic 0.
X. Power Gating Cells :
There are several power gating cells available in standard cell library for low power and multi-voltage designs.
Power gating cells are: Level shifter, Isolation cell, Retention register, Power switches, and multi-Vt cells.
Detailed description about these cells will provide in Low-Power section in future.
Bounds - Significance and Types
A placement bound can be used to place a group of cells together within the specified region. Bounds can be used when cells in the same hierarchy/module are placed far from each other by placement tool, which is termed as module splitting in technical term. By creating bound we can place these cells closer to each other and can achieve better QoR in terms of routing, timing, and IR drop results.
While creating module one must specify enough area according to number of instances being grouped together and leave some extra space for buffering during optimisation. Otherwise can lead to more congestion and cell density. Standard practice is to keep bound utilisation around 50% to 55%. One can adjust bound utilisation based upon the design requirement.
There are three types of bound - Soft, Hard, and Exclusive.
Soft Bound does not forces all the cells, grouped together, to be placed in bound only. Few cells from the group may be placed outside of bound based upon their connection with other objects. Cells from other group can also be placed within the bound. In short this is the most flexible type of bound.
Hard Bound is completely opposite of soft bound. It neither allows cells from bound to go outside of the bound nor does it allows cells from outside group to place within the bound. Hard bound should be created very carefully and only if it is extremely required because sometimes hard bounds can lead to cell overlap issue and a poor placement QoR due to its rigid attribute.
Exclusive Bound is like a partial bound wherein cells defined within the bound group are not allowed to place outside of the bound but cells from other groups can be placed inside the boundaries of the bound.
Placement Blockage - Significance and Types
Placement blockages are used to restrict the placement of cells at specified region either completely or partially. Placement blockages can be defined strategically in order to achieve better congestion and density QoR. Congestion and density reports should be thoroughly analysed prior to create a placement blockage by doing so designer can get exact idea where to create the placement blockage. Otherwise placement QoR will degrade instead of improving it.
Based upon its nature, placement blockages can be broadly categorised into three types - Hard, Soft, and Partial.
Hard placement blockage is one which prevents any cell or macro to be placed within the specified boundary during placement, legalization, and optimisation stages. This type of placement blockage can be used only when there is a requirement to place any specific cell at a particular location. Requirement to place such cells may come from chip-top level, designer level, or foundry level. Hard placement blockage can also be used in very narrow macro channels where cells are not suppose to be placed.
Soft placement blockage is one which blocks the placement of cells/macros within the specified region during initial placement stage but can allow placement of cells during legalization and optimisation stages. This type of placement blockage is used to control the placement of too many cells at a particular area. For example, if more number of cells are getting placed near macro edges then it can lead to more congestion. In such situation it is advisable to use soft placement blockage.
Partial placement blockage permits to occupy only specified percentage of area during coarse placement stage but can occupy more area during legalization and optimisation stages. A partial placement blockage with 30% blocked area will allow only 70% utilisation in the specified region. Partial placement blockage is used to control the cell density at a particular area in the block. Partial placement blockage is also termed as density screen. This type of blockage can be very helpful to achieve better congestion and IR drop results.
Apart from these three types of blockages, few PnR tools also allow a type of blockage wherein only buffers and inverters are allowed to place. Such blockages can be used in macro channel and near to ports for buffering purpose.
Cell Padding/Keepout margin
Padding is nothing but to specify a small region around a standard cell within which any other cell is not allowed to be placed. It acts as hard placement blockage surrounding the standard cells. PnR tools allows to create keepout margin either on any one side of the cell or on all four sides. It depends upon the design requirement that on which side keepout margin to be specified. Defining keepout margin can be helpful to control cell density or pin density.
Padding can be defined at three levels as described below:
Instance padding, in which designer can specify extra margin for the group of instances.
Cell padding, in which designer can specify extra margin for a particular library cell and same will be applied for all the instances of that library cell. For example, specifying keepout margin for a 2-input X-OR gate will be applied for all the instances of 2-input X-OR gate in the design.
Module padding, in which designer is allowed to specify extra margin for all the standard cells belonging to a module or a sub-module in the design.
Based upon the design requirement one can choose which type of padding to be used.
In this blog, I have tried to cover the concepts using which one can achieve a better placement QoR. Entire placement result depends upon how well we can use placement constraints described in this post. Hope you find this post informative. Please feel free to provide your feedback or to come up with any query. Will see you soon with another piece of information till then Stay Happy, Stay Safe...!! :)
Thank you very much sir, it is clearly understandable.😊