Routing is the final stage in PnR flow. Once our design is placed and the clock tree is built now it is the time to connect all the devices with each other as per connections in the netlist. In short, we can say that the process of connecting the cells in the design is called routing. In this blog, the below topics will be discussed.
Goal of routing
Pre-requisites for routing
Terminologies related to routing
How routing is performed in PnR tool
Analyzing the routing results
Inputs and outputs of the routing stage
Goal of Routing
The main purpose of routing stage is to:
To set up the connectivity across cells according to netlist
To ensure routes are not detoured
To avoid open and short circuits of nets
To completely connect the design with minimum numbers of DRC and LVS violations
To reduce the signal integrity issues among the nets having higher switching activity
To meet PPA requirements
Pre-requisites for Routing
Before proceeding for routing one must ensure that the following parameters are met.
All the base DRC violations should be clean
Design is placed without any legality issues
Power routing is properly done and connected with the PG pins of the cells
Any signal pin should not lie below power rails as it may remain unconnected or it can create a short with PG rail
Clock tree is built and optimized
Technology LEF file should define all the routing rules. PnR tool gets all the information regarding routing from Tech LEF file
Congestion, transition, capacitance, skew, latency, and timing values should be within an acceptable range
Check all the settings related to routing stages
Routing blockages and routing guides are defined as per design requirement
Routing Terminologies
Before proceeding for routing implementation in the PnR tool let us first get familiar with some important terminologies related to the routing.
Routing track is the imaginary path on which actual metal layers can be drawn. Tracks are created during the floorplanning stage itself. Used to calculate congestion during global routing in placement and CTS stage. Routing tracks are also termed as routing resources.
Pitch is defined as the horizontal (vertical) distance between two vertical (horizontal) tracks. Pitch values are decided from the min spacing rule of a particular metal layer. Pitch is different for each metal layer. An example of the routing track and pitch is shown in figure 1.
The Routing region is the space in the core region of a chip available for routing. Regions where macros and standard cells are placed generally act as blockages for the routing nets.
The Routing channel is a narrow routing region in the space between macros. In some cases, space between macros is deliberately kept for the routing purpose. The routing channel can be either horizontal or vertical. A horizontal routing channel is indicated by black lines in figure 2.
Grid cells are small partitions created in a block during global routing. These are imaginary partitions, not the physical partition. Congestion is calculated based upon the number of tracks passing through a grid and the number of actual metal wires required in that particular grid. Grid cells are indicated by blue boxes in figure 2.
A net is a connection between two or more interconnected pins. The connection of these nets is defined in netlist and based upon that metal wires are laid in the design. A net is also known as wire.
A port in physical design is a pin or a group of pins from where the signal can enter or can go out of the block.
A pin is a physical connection where the net can be attached to the cell.
Routing Implementation
In any PnR tool, there are three major steps involved in performing routing of the design. These steps are Global routing, Track assignment, and Detail routing. One more type of routing is allowed in PnR tools during ECO stage viz. ECO routing. Each of these steps is discussed below.
1. Global Routing :
This is the initial stage of routing. The main purpose of global routing is to determine whether the design is routable or not. Designers can also get an idea about the congestion from global routing itself. The global routing process is less time consuming as it performs coarse-grain routing. Generally there are three phases involved in global routing namely defining routing regions, region assignment, and pin assignment
In the first phase global router divides entire block into small grid cells generally termed as global routing cells (gcells). These grid cells should be in the multiple of site height (site row) and site width. Each gcell has a finite limit of how many nets can pass through itself. This capacity is defined by the number of routing tracks that can be accommodated in a gcell. Based upon the number of tracks available and number of nets passing through the gcell, global router calculates overflow in a gcell. A positive overflow means congestion.
Overflow = Nets passing from a gcell (Demand) - Number of tracks available (Supply)
In the second phase, each net is assigned with a routing region but the physical layout of wire is not done yet. Major goal of this phase is to determine that which net will pass through which region. This phenomenon of assigning nets to the region should be both timing and congestion aware. In the third phase, these nets are assigned to the pins where it has to be connected. In this way, global routing prepares a complete plan of how metal layers will be physically laid-off in detail routing stage.
Routing blockages and routing guides play a very important role in global routing. It can affect congestion and route length parameters. Multiple iterations are performed for global routing. Iteration by iteration tool tries to optimize the routing congestion and timing as defined in settings prior to start the global routing stage. Designers can increase either congestion effort or timing effort based upon design requirements. After each iteration global router generates a summary report stating congestion, route length, and via count.
NOTE: In order to reduce some turn around time, keep a constant look into log file while global routing is going on. From the summary report, one can get an idea of whether thee desired congestion value is achieved or not. If not achieved then the designer can immediately start a new iteration with necessary changes instead of waiting for the detail route to get complete. This strategy can be implemented during the placement stage as well.
2. Track Assignment :
After global routing, the next step that tool performs is assigning tracks to each net. For assigning tracks tool uses the coarse route performed at the global routing stage. In the global routing stage, the tool calculates the number of tracks available in each gcell and the number of wires passing through that gcell. Now at this stage, each wire is assigned to a track either horizontally or vertically. In this process, the tool removes overlap in the nets.
Track assignment does not perform any timing optimization or DRC fixing by default. This optimization is carried out in the detail routing stage. Same as global routing, track assignment also creates a summary report at the end of the run. It reports about the number of wires in each metal layer, their net length, and via count.
3. Detail Routing :
In the detail routing stage, actual metal wires are placed according to information developed in global routing and track assignment stages. Gcells generated in global routing stage are reused here and wires are routed based upon the track assigned to it. This is a fine-grain routing process. Tool only considers a small area for routing at a time. The region having more number of nets or the most critical region is given higher priority in detail routing. Then regions with lesser criticality or with less number of wires are routed. This process helps in reducing congestion as tracks from neighboring regions, where wires are less compared to available tracks, can be utilized to connect pins in current region. With this strategy, detail routing optimizes the congestion.
Detail routing performs incremental optimization which means it performs multiple iterations by taking input from previous iteration and further improves the QoR. Detail routing is timing and congestion aware. To optimize timing detail router tries to route the net with the shortest possible distance between pin connection. This also helps in reducing IR drop due to large wires. If the router is not getting a shorter path then in some cases it can also move certain cells (unless don't touch is specified on the cell) during optimization to fix timing issues. Along with timing, the router also fixes shorts. It removes shorts by removing the shorting nets and reroute them. Still, in very congested design, the tool cannot fix shorts at all the locations.
Another important parameter that detail router optimizes is DRC violations. DRC rules are described in the tech LEF file. Apart from DRC rules, the detail router also takes care of NDR rules for critical nets. Thus, we can add one more optimization parameter in detail routing and that is signal integrity. This helps in eliminating cross-talk effects.
As too many optimizations are performed in detail routing, run time for it his very high. Designs with multi-million gates can take up to a few days to complete detail routing and optimization. Thus, the designer needs to be very focused while starting runs for routing. Even a small mistake can delay the project cycle by a few days. It is always advisable to monitor run at regular interval of time for any critical errors or warnings.
4. ECO Routing :
All the above routing steps give us a routed design. Even after performing so much optimization, any PnR tool has certain limitations in fixing the issues. The tool cannot provide us completely clean design. There are many issues that we have to fix manually. For this, we perform the ECO (Engineering Change Order) stage. In this stage, the floorplan of the design gets freeze and we have very little options to clean the design. Regarding this will discuss in a separate blog.
As we have already seen there is a lot of things happening in the routing stage. So it is not advisable to run entire routing all the time we make any small changes in the design. It will only push the project deadline. In order to meet this challenge, tool gives us the option to perform routing only in a specific region where changes are done. Entire other routing is untouched. This process is called ECO routing. ECO routing also performs timing and DRC optimization but its run time is quite less compared to detail routing.
Analyzing the Routing Data
Routing is performed form the initial stages of PD cycle. At the initial stage, the main purpose to perform routing is to check the design congestion which will help us to reduce the number of shorts in the design. Considering all the stages below are some checks one need to perform once routing is completed.
Check for congestion (esp. after placement and CTS stage)
Check for short and open nets after detail routing
Check for any long routes and detour nets
Setup and hold timing checks
Max tran, max cap, and max fanout checks
The tool will not be able to fix all the DRC violations. Check and fix the remaining violations
Check Layout Versus Schematic (LVS). This check is done to ensure the functionality of the routed design is same as provided by the designer
Perform Electric Rule Check (ERC). ERC checks for any PG short circuit or open circuit
Inputs and Outputs of Routing Stage
Below is the list of input files required to begin with routing.
Post CTS DEF and netlist files
Tech LEF and cell LEF files
SDC file
LIB file
Don't use and don't touch list
Some important output files from the routing stage are as below.
Routed DEF and netlist
Congestion report
DRC, LVS reports
Timing reports
RC extraction file
Back annotated delay file (Standard Delay Format)
In this blog, I have tried to cover almost all the important topics on routing in physical design. If anything missed or for any query please feel free to reach out. Stay safe, stay happy... :)
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