Hello Readers...!
Sanity check is a basic test to evaluate the design inputs. It is always advisable to run the sanity check before starting the PnR flow. This will ensure designer that the input files required for the physical implementation are accurate and any mismatch does not exist.
At the backend stage, mainly four types of sanity checks are performed.
1. Library Check
2. Design (or Netlist) Check
3. Constraints Check
4. Timing Check
1. Library Check:
There are two types of libraries available for physical implementation and they are physical (lef) and logical libraries (lib). For each cell used in the design (netlist), its physial and logical information must be present in the respective libraries. So basic idea of performing this test is to check there is a consistency between physical and logical library.
If any particular cell used in the design does not have LEF view or missing any timing/power/logic information than we can resolve the issue at this stage itself. Command to perform library check is check_library
2. Design (or Netlist) Check
The purpose of this test is to check that the netlist provided by the front-end team is unique and accurate. By unique netlist it means that there is only one main module in the design. Other checks carried out are:
Floating nets and/or input pins
Unconnected output pins
Multi-driven net/pin
Unconstrained pins
Don't use or don't touch cell used in the design
Combinational path having a loop
To run this check use the following command after reading in the netlist in PnR tool:
check_design
3. Constraints Check
To calculate the timing of a path, it has to be constrained. This test is performed to check that all paths on which timing analysis has to be carried out are constrained. Below issues can be captured with the constraints check:
Clock not reaching the clock pin of the sequential cell
Input/Output delay not defined on any IO port
Input/Output port missing the slew or load information
Ideal clock waveform
Unconstrained endpoints
Missing or inappropriate clock definition in SDC file
Multiple clock driving the same sequential cell
Command to check for the missing constraint is check_timing
4. Timing Check
Prior to kick-start the PnR flow it is important to check the critical path timing in the design. If timing is too bad at this stage than PnR tool will end up by adding a lot of buffers/inverters to converge the violating paths. If any architecture change is required in the design, it can be evaluated at this stage itself. Command to check timing at pre-place stage is:
time_design -pre_place